The present invention relates in general to technology for the manufacture of a semiconductor integrated circuit device, and, more particularly, to a technique that is effective when applied to electrical testing of a semiconductor integrated circuit device having a plurality of electrode pads disposed at narrow pitches.
For example, in the burn-in test of a semiconductor device having a protruding electrode, using a semiconductor device testing apparatus having a plurality of pyramid-shaped contact terminals protruding toward the semiconductor device, at least one contact terminal is brought into contact, at the ridge line or slope thereof, with one of the protruding electrodes, thereby bringing the semiconductor device into electrical contact with the semiconductor device testing apparatus and preventing damage to the protruding electrode during contact of the protruding electrode with the contact terminal (for example, refer to Japanese Unexamined Patent Publication No. 2002-14137.)
In addition, there is a technology for providing a probe, which is held by a support, for use in testing the electrical properties of a semiconductor wafer by bringing the probe into contact with a bump electrode of the semiconductor wafer. The probe is provided with a first contact terminal for applying a voltage to the bump electrode of the semiconductor wafer, a first insulating member encompassing the first contact terminal, a second contact terminal encompassing the first insulating member and used for detecting a voltage through the bump electrode, and a second insulating member interposed between the first and second contact terminals. Each of the first and second contact terminals has first and second terminal portions and first and second coil springs interposed between the first and second terminal portions, whereby a deviation of the probe from the bump electrode can be prevented even if the minimization of the bump electrode proceeds (for example, refer to Japanese Unexamined Patent Publication No. 2002-228682).
There also is a technology for electrically connecting integrated circuit devices fabricated in a semiconductor wafer to a testing and measuring apparatus by bringing a connection terminal of a needle of a probe into contact with a bump electrode of the integrated circuit devices, pressing the bump electrode of the adjacent integrated circuit device in the wafer to cause deformation of the tip portion of the bump electrode and thereby making the heights of the bump electrodes uniform, whereby integrated circuit devices having bump electrodes equal in their height are connected to the testing measuring apparatus via the probe at a uniform contact resistance so as to improve the test accuracy and cause fluctuations in connection resistance between the integrated circuit device and an assembly substrate to be reduced (for example, refer to Japanese Unexamined Patent Publication No. Hei 5 (1993)-283490).
There also is a technology, in which a contactor is used for testing electrical properties of a wafer by bringing a plurality of solder balls formed over a semiconductor wafer into contact with a plurality of probes corresponding to them and transmitting/receiving signals with a tester side. Each probe is provided with, as a contact terminal, a cylindrical portion capable of making conduction-free contact with the solder ball at the outside of the center thereof, whereby the contacting of the probe with the solder ball does not cause damage at the center of the solder ball, and the reflow process of the solder ball can be omitted (for example, refer to Japanese Patent Laid-Open No. 2001-108706).